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基本信息

书名：FPGA芯片架构设计与实现

定价：56.00元

作者：余乐

出版社：电子工业出版社

出版日期：2017-07-01

ISBN：9787121306105

字数：

页码：

版次：1

装帧：平装-胶订

开本：16开

商品重量：0.4kg

编辑推荐

内容提要

可编程通用逻辑门阵列芯片简称FPGA，与CPU，DSP并列为三大通用数字处理芯片，广泛应用于通信、航空航天、医疗、国防军工以及安防视频监控等领域。通过本书的学习，读者可以全面了解一颗FPGA芯片从设计、验证到流片的开发过程。 本书共分10章，采取“总—分”的编排方式。章从架构的总体设计入题对FPGA进行介绍。第2~10章，分别对其中的各个重要模块逐一介绍，包括：时钟网络、电源/地线网络和漏电流、可编程逻辑单元、可编程I/O模块、DDR存储器接口、数字延时锁定环、连线连接盒、互连线段长度分布以及配置模块。 本书适合从事集成电路设计的工程师、微电子专业高年级研究生以及从事微电子专业教学研究的教师和科研人员阅读。本书还可以作为高等院校教授集成电路设计的辅助资料。

目录

章 FPGA 架构总体设计 ········································································· 1
1.1 FPGA 芯片研制流程·········································································· 1
1.2 FPGA 架构设计流程·········································································· 7
1.3 FPGA 规模和资源划分 ····································································· 17
1.4 FPGA 中功能模块划分 ····································································· 20
本章参考文献 ······················································································ 26
第2 章 FPGA 中时钟网络 ·········································································· 30
2.1 简介 ···························································································· 30
2.2 FPGA CDN 建模 ············································································· 33
2.3 时钟网络设计方法 ·········································································· 43
2.4 时钟网络的灵活性 ·········································································· 48
2.5 路由级联 ······················································································ 51
2.6 仿真实验 ······················································································ 55
2.7 时钟网络热学建模 ·········································································· 61
2.8 仿真实验 ······················································································ 62
本章参考文献 ······················································································ 66
第3 章 FPGA 中电源/地线网络和漏电流 ······················································· 68
3.1 电源/地线网络 ··············································································· 68
3.2 IR-DROP 分析与优化 ········································································ 71
3.3 漏电流组成 ··················································································· 73
3.4 降低漏电流的方法 ·········································································· 74
3.5 基于VIA 分布的IR-DROP 分析 ··························································· 77
3.6 仿真实验 ······················································································ 81
3.7 不均匀测试点的IR-DROP 求解 ··························································· 87
3.8 FPGA 电源网络IR-DROP 分析 ···························································· 89
本章参考文献 ······················································································ 94
第4 章 FPGA 中可编程逻辑单元 ································································· 98
4.1 基于多路选择器的逻辑单元 ······························································ 98
4.2 基于四输入LUT 的可编程逻辑单元的设计 ·········································· 102
4.3 LUT 的模型与实现 ········································································ 103
4.4 LUT 的输入数目K 的确定 ······························································· 106
4.5 进位逻辑 ····················································································· 109
4.6 基于查找表结构的FPGA 的不足 ······················································· 115
4.7 AIC 结构逻辑簇 ············································································ 117
4.8 基于AIC 结构FPGA 的逻辑簇 ························································· 120
4.9 面向AIC 的映射工具及结构评估平台 ················································ 124
4.10 结构特征匹配的AIC 簇互连优化 ···················································· 125
4.11 仿真分析和比较 ·········································································· 131
本章参考文献 ····················································································· 133
第5 章 FPGA 中可编程I/O 模块 ································································· 136
5.1 可编程I/O 系统结构 ······································································ 136
5.2 IOE 中的可编程输入缓冲器设计 ······················································· 138
5.3 IOE 中的可编程输出缓冲器设计 ······················································· 144
5.4 可编程I/O 的后端版图设计······························································ 156
5.5 高可靠I/O 模块的后端版图与测试 ····················································· 166
5.6 可编程I/O 的供电策略 ··································································· 172
5.7 全芯片IO 的ESD 技术 ····················································

作者介绍

申请人于2009年3月至2012年8月在中科院电子所可编程芯片与系统研究室攻读博士学位，从事下一代SOC FPGA的关键集成技术研究。博士课题来源于中科院/国家外专局的创新团队国际合作伙伴计划'片上可编程系统前沿技术研究”。博士毕业获微电子与固体电子学博士学位。同年，以申请人博士论文为基础，帮助实验室申请了国家自然科学基金面上项目'基于TSV互连的三维FPGA架构及关键技术研究”。2012年博士毕业后，选择留所继续从事博士后研究工作，并作为国自基金项目的实际负责人，管理项目的整体推进，指导学生完成了2篇论文的投稿。博士后期间，参与了两款FPGA芯片的研制工作，分别是0.13um 百万门级FPGA（中科院重点方向性项目）和40nm FPGA-ip核（国家重大专项）。2015年博士后出站，出站报告'FPGA时钟分布网络研究”从延时、面积、功耗、灵活性以及热性能等多方面，对FPGA的关键架构技术进行了研究。

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