基本信息

书名：现代VLSI设计：片上系统设计(第3版)(改编版)

定价：48.20元

作者：沃尔夫

出版社：高等教育出版社

出版日期：2006-02-01

ISBN：9787040182552

字数：

页码：604

版次：1

装帧：平装

开本：16开

商品重量：0.4kg

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内容提要

《现代VLSI设计：片上系统设计（第3版改编版）》是一本介绍现代VLSI芯片设计过程的书籍，改编自PEARSONEDUCATION出版的ModerVLSI Design：System-on-Chip Design（3／e）一书。书中全面地论述了VLSI芯片设计的有关问题，反映了目前SoC的新进展，并介绍了SoC的设计方法。全书共分10章。内容包括：数字系统与VLSl，晶体管的版图设计，逻辑门，组合逻辑网络，时序电路，子系统设计，自顶向下设计，系统设计，芯片设计，CAD系统及算法，另有3个附录。每章末尾均附有难度不同的习题。附录中还提供了丰富而实用的词汇表。改编者保持原书的风格和原有体系结构，根据的教学要求和课程设置，调整了原书的一些内容，使之更适合我国高等学校作为教材使用。
《现代VLSI设计：片上系统设计（第3版改编版）》可作为高校电子工程、计算机科学与工程、微电子半导体等专业的高年级本科生和研究生的教材或教学参考书，也可供从事芯片设计的工程技术人员作为参考书使用。

目录

Preface to the Third Editioix
Preface to the Second Editioxi
Preface xiii
1 Digital Systems and VLSI 1
1.1 Why DesigIntegrated Circuits 1
1.2 Integrated Circuit Manufacturing 4
1.2.1 Technology 4
1.2.2 Economics 6
1.3 CMOS Technology 15
1.3.1 CMOS Circuit Techniques 15
1.3.2 Power Consumptio16
1.3.3 Desigand Testability 17
1.4 Integrated Circuit DesigTechniques 18
1.4.1 Hierarchical Desig19
1.4.2 DesigAbstractio22
1.4.3 Computer-Aided Desig28
1.5 A Look into the Future 30
1.6 Summary 31
1.7 References 31
1.8 Problems 32

2 Transistors and Layout 33
2.1 Introductio33
2.2 FabricatioProcesses 34
2.2.1 Overview 34
2.2.2 FabricatioSteps 37
2.3 Transistors 40
2.3.1 Structure of the Transistor 40
2.3.2 A Simple Transistor Model 45
2.3.3 Transistor Parasitics 48
2.3.4 Tub Ties and Latchup 50
2.3.5 Advanced Transistor Characteristics 53
2.3.6 Leakage and Subthreshold Currents 60
2.3.7 Advanced Transistor Structures 61
2.3.8 Spice Models 61
2.4 Wires and Vias 62
2.4.1 Wire Parasitics 65
2.4.2 SkiEffect iCopper Interconnect 72
2.5 DesigRules 74
2.5.1 FabricatioErrors 75
2.5.2 Scalable DesigRules 77
2.5.3 SCMOS DesigRules 79
2.5.4 Typical Process Parameters 83
2.6 Layout Desigand Tools 83
2.6.1 Layouts for Circuits 83
2.6.2 Stick Diagrams 88
2.6.3 Layout Desigand Analysis Tools 90
2.6.4 Automatic Layout 94
2.7 References 97
2.8 Problems 97

3 Logic Gates 105
3.1 Introductio105
3.2 Static Complementary Gates 106
3.2.1 Gate Structures 106
3.2.2 Basic Gate Layouts 110
3.2.3 Logic Levels 113
3.2.4 Delay and TransitioTime 118
3.2.5 Power Consumptio127
3.2.6 The Speed-Power Product 130
3.2.7 Layout and Parasitics 131
3.2.8 Driving Large Loads 134
3.3 Switch Logic 135
3.4 Alternative Gate Circuits 136
3.4.1 Pseudo-nMOS Logic 137
3.4.2 DCVS Logic 139
3.4.3 Domino Logic 141
3.5 Low-Power Gates 146
3.6 Delay Through Resistive Interconnect 152
3.6.1 Delay Through aRC TransmissioLine 152
3.6.2 Delay Through RC Trees 155
3.6.3 Buffer InsertioiRC TransmissioLines 159
3.6.4 Crosstalk BetweeRC Wires 161
3.7 Delay Through Inductive Interconnect 164
3.7.1 RLC Basics 165
3.7.2 RLC TransmissioLine Delay 166
3.7.3 Buffer InsertioiRLC TransmissioLines 167
3.8 References 169
3.9 Problems 171

4 Combinational Logic Networks 177
4.1 Introductio177
4.2 Standard Cell-Based Layout 178
4.2.1 Single-Row Layout Desig179
4.2.2 Standard Cell Layout Desig188
4.3 Simulatio190
4.4 Combinational Network Delay 194
4.4.1 Fanout 195
4.4.2 Path Delay 196
4.4.3 Transistor Sizing 201
4.4.4 Automated Logic Optimizatio210
4.5 Logic and Interconnect Desig211
4.5.1 Delay Modeling 212
4.5.2Wire Sizing 213
4.5.3 Buffer Insertio214
4.5.4 Crosstalk Minimizatio216
4.6 Power Optimizatio221
4.6.1 Power Analysis 221
4.7 Switch Logic Networks 225
4.8 Combinational Logic Testing 229
4.8.1 Gate Testing 231
4.8.2 Combinational Network Testing 234
4.9 References 236
4.10 Problems 236

5 Sequential Machines 241
5.1 Introductio241
5.2 Latches and Flip-Hops 242
5.2.1 Categories of Memory Elements 242
5.2.2 Latches 244
5.2.3 Flip-Flops 251
5.3 Sequential Systems and Clocking Disciplines 252
5.3.1 One-Phase Systems for Flip-Flops 255
5.3.2 Two-Phase Systems for Latches 257
5.3.3 Advanced Clocking Analysis 265
5.3.4 Clock Generatio272
5.4 Sequential System Desig273
5.4.1 Structural Specificatioof Sequential Machines 273
5.4.2 State TransitioGraphs and Tables 275
5.4.3 State Assignment 284
5.5 Power Optimizatio290
5.6 DesigValidatio291
5.7 Sequential Testing 293
5.8 References 300
5.9 Problems 300

6 Subsystem Desig303
6.1 Introductio303
6.2 Subsystem DesigPrinciples 306
6.2.1 Pipelining 306
6.2.2 Data Paths 308
6.3 Combinational Shifters 311
6.4 Adders 314
6.5 ALUs 321
6.6 Multipliers 322
6.7 High-Density Memory 331
6.7.1 ROM 333
6.7.2 Static RAM 335
6.7.3 The Three-Transistor Dynamic RAM 339
6.7.4 The One-Transistor Dynamic RAM 340
6.8 References 344
6.9 Problems 344

7 Floorplanning 347
7.1 Introductio347
7.2 Floorplanning Methods 348
7.2.1 Block Placement and Channel Definitio352
7.2.2 Global Routing 358
7.2.3 Switchbox Routing 360
7.2.4 Power Distributio361
7.2.5 Clock Distributio364
7.2.6 Floorplanning Tips 369
7.2.7 DesigValidatio370
7.3 Off-Chip Connections 371
7.3.1 Packages 371
7.3.2 The I/O Architecture 375
7.3.3 Pad Desig376
7.4 References 379
7.5 Problems 381

8 Architecture Desig387
8.1 Introductio387
8.2 Hardware DescriptioLanguages 388
8.2.1 Modeling with Hardware DescriptioLanguages 388
8.2.2 VHDL 393
8.2.3 Verilog 402
8.2.4 C as a Hardware DescriptioLanguage 409
8.3 Register-Transfer Desig410
8.3.1 Data Path-Controller Architectures 412
8.3.2ASM Chart Desig413
8.4 High-Level Synthesis 422
8.4.1 Functional Modeling Programs 424
8.4.2 Data 425
8.4.3 Control 435
8.4.4 Data and Control 441
8.4.5 DesigMethodology 443
8.5 Architectures for Low Power 444
8.5.1 Architecture-DriveVoltage Scaling 445
8.5.2 Power-DowModes 446
8.6 Systems-on-Chips and Embedded CPUs 447
8.7 Architecture Testing 453
8.8 References 457
8.9 Problems 457

9 Chip Desig461
9.1 Introductio461
9.2 DesigMethodologies 461
9.3 KitcheTimerChip 470
9.3.1 Timer Specificatioand Architecture 471
9.3.2 Architecture Desig473
9.3.3 Logic and Layout Desig478
9.3.4 DesigValidatio485
9.4 Microprocessor Data Path 488
9.4.1 Data Path Organizatio489
9.4.2 Clocking and Bus Desig490
9.4.3 Logic and Layout Desig492
9.5 References 494
9.6 Problems 495

10 CAD Systems and Algorithms 497
10.1 Introductio498
10.2 CAD Systems 498
10.3 Switch-Level Simulatio499
10.4 Layout Synthesis 501
10，4，1 Placement 503
10.4.2 Global Routing 506
10.4.3 Detailed Routing 508
10.5 Layout Analysis 510
10.6 Timing AnalysisandOptimizatio512
10.7 Logic Synthesis 517
10.7.1 Technology-Independent Logic Optimizatio518
10.7.2 Technology-Dependent Logic Optimizations 525
10.8 Test Generatio528
10.9 Sequential Machine Optimizations 530
10.10 Scheduling and Binding 532
10.11 Hardware/Software Co-Desig534
10.12 References 535
10.13 Problems 535
A Chip Designers Lexico539
B Chip DesigProjects 557
B.1 Class Project Ideas 557
B.2 Project Proposal and Specificatio558
B.3 DesigPla559
B.4 DesigCheckpoints and Documentatio562
B.4.1 Subsystems Check 563
B.4.2 First Layout Check 563
B.4.3 Project Completio563
C KitcheTimer Model 565
C.1 Hardware Modeling iC 565
C.I.1 Simulator 567
C.1.2 Sample Executio573
References 577
Index 593

作者介绍

文摘

A register-transfer simulator exhibits the correct cycle-by-cycle behavior atits inputs and outputs， but the internal implementatioof the simulator mayhave nothing to do with the logic implementation. Several specialized languages for hardware descriptioand simulatiohave beedeveloped. Hardware simulatiolanguages， such as VHDL and Vefilog， provide primitiveswhich model the parallelism of logic gate evaluation， delays， etc.， so that astructural descriptiolike a list automatically provides accurate simulation. Ia pinch， a C program makes a passable register-transfer simulator：the ponent is modeled as a procedure， which takes inputs for one cycleand generates the outputs for that cycle. However， hardware modeling iCor other general-purpose programming languages 现代VLSI设计：片上系统设计(第3版)(改编版) 9787040182552 高等教育出 电子书 下载 mobi epub pdf txt